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general description the max7315 i 2 c-/smbus-compatible serial interfaced peripheral provides microprocessors with 8 i/o ports. each i/o port can be individually configured as either an open-drain current-sinking output rated at 50ma at 5.5v, or a logic input with transition detection. a ninth port can be used for transition detection interrupt or as a general- purpose output. the outputs are capable of directly dri- ving leds, or providing logic outputs with external resistive pullup up to 5.5v. pwm current drive is integrated with 8 bits of control. four bits are global control and apply to all led outputs to provide coarse adjustment of current from fully off to fully on in 14 intensity steps. each output then has indi- vidual 4-bit control, which further divides the globally set current into 16 more steps. alternatively, the current control can be configured as a single 8-bit control that sets all outputs at once. the max7315 is pin and software compatible with the pca9534 and pca9554(a). each output has independent blink timing with two blink phases. all leds can be individually set to be on or off during either blink phase, or to ignore the blink control. the blink period is controlled by a register. the max7315 supports hot insertion. all port pins, the int output, sda, scl, and the slave address inputs ado-2 remain high inpedance in power-down (v+ = 0v) with up to 6v asserted upon them. the max7315 is controlled through the 2-wire i 2 c/smbus serial interface, and can be configured to one of 64 i 2 c addresses. applications features ? 400kbps, 2-wire serial interface, 5.5v tolerant ? 2v to 3.6v operation ? overall 8-bit pwm led intensity control global 16-step intensity control plus individual 16-step intensity control ? automatic two-phase led blinking ? 50ma maximum port output current ? supports hot insertion ? outputs are 5.5v-rated open drain ? inputs are overvoltage protected to 5.5v ? transition detection with interrupt output ? low standby current (1.2? typ; 3.3? max) ? tiny 3mm x 3mm, thin qfn package ? -40? to +125? temperature range ? all ports can be configured as inputs or outputs max7315 8-port i/o expander with led intensity control, interrupt, and hot-insertion protection ________________________________________________________________ maxim integrated products 1 12 11 10 9 int/o8 p7 p6 5 6 7 8 p3 gnd p5 16 15 14 13 ad1 ado v+ 1234 ad2 p0 p1 p2 sda p4 scl thin qfn top view max7315ate pin configurations 19-3056; rev 3; 1/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information part temp range pin- package top mark pkg code max7315ate -40 c to +125 c 16 thin qfn 3mm x 3mm x 0.8mm aau t1633-4 max7315aee -40 c to +125 c 16 qsop m ax 7315au e -40 c to +125 c 16 tssop pin configurations continued at end of data sheet. lcd backlights led status indication portable equipment laptop computers keypad backlights rgb led drivers cellular phones purchase of i 2 c components of maxim integrated products, inc., or one of its sublicensed associated companies, conveys a license under the philips i 2 c patent rights to use these compo- nents in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. typical application circuit appears at end of data sheet.
max7315 8-port i/o expander with led intensity control, interrupt, and hot-insertion protection 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage (with respect to gnd) v+ .............................................................................-0.3v to +4v scl, sda, ad0, ad1, ad2, p0?7 ..........................-0.3v to +6v int /o8 .....................................................................-0.3v to +8v dc current on p0?7, int /o8 ............................................55ma dc current on sda.............................................................10ma maximum gnd current ....................................................190ma continuous power dissipation (t a = +70?) 16-pin tssop (derate 9.4mw/? over +70?) ............754mw 16-pin qsop (derate 8.3mw/? over +70?)..............666mw 16-pin qfn (derate 14.7mw/? over +70?) ............1176mw operating temperature range (t min to t max )-40? to +125? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? electrical characteristics (typical operating circuit, v+ = 2v to 3.6v, t a = t min to t max , unless otherwise noted. typical values are at v+ = 3.3v, t a = +25?.) (note 1) parameter symbol conditions min typ max units operating supply voltage v+ 2 3.6 v output load external supply voltage v ext 0 5.5 v t a = +25? 1.2 2.3 t a = -40? to +85? 2.6 standby current (interface idle, pwm disabled) i + s c l and s d a at v + ; other d i g i tal i np uts at v + or gn d ; p wm i ntensi ty contr ol d i sab l ed t a = t min to t max 3.3 ? t a = +25? 7 12.1 t a = -40? to +85? 13.5 supply current (interface idle, pwm enabled) i + s c l and s d a at v + ; other d i g i tal i np uts at v + or gn d ; p wm i ntensi ty contr ol enab l ed t a = t min to t max 14.4 ? t a = +25? 40 76 t a = -40? to +85? 78 supply current (interface running, pwm disabled) i + f scl = 400khz; other digital inputs at v+ or gnd; pwm intensity control disabled t a = t min to t max 80 ? t a = +25? 51 110 t a = -40? to +85? 117 supply current (interface running, pwm enabled) i + f scl = 400khz; other digital inputs at v+ or gnd; pwm intensity control enabled t a = t min to t max 122 ? input high voltage sda, scl, ad0, ad1, ad2, p0?7 v ih 0.7 ? v+ v input low voltage sda, scl, ad0, ad1, ad2, p0?7 v il 0.3 ? v+ v input leakage current sda, scl, ad0, ad1, ad2, p0?7 i ih , i il input = gnd or v+ -0.2 +0.2 a input capacitance sda, scl, ad0, ad1, ad2, p0?7 8pf
max7315 8-port i/o expander with led intensity control, interrupt, and hot-insertion protection _______________________________________________________________________________________ 3 electrical characteristics (continued) (typical operating circuit, v+ = 2v to 3.6v, t a = t min to t max , unless otherwise noted. typical values are at v+ = 3.3v, t a = + 25?.) (note 1) parameter symbol conditions min typ max units t a = +25? 0.15 0.25 t a = -40? to +85? 0.29 v+ = 2v, i sink = 20ma t a = t min to t max 0.31 t a = +25? 0.13 0.22 t a = -40? to +85? 0.25 v+ = 2.5v, i sink = 20ma t a = t min to t max 0.27 t a = +25? 0.12 0.22 t a = -40? to +85? 0.23 output low voltage p0?7, int /o8 v ol v+ = 3.3v, i sink = 20ma t a = t min to t max 0.25 v output low-voltage sda v olsda i sink = 6ma 0.4 v pwm clock frequency f pwm 32 khz timing characteristics (typical operating circuit, v+ = 2v to 3.6v, t a = t min to t max , unless otherwise noted. typical values are at v+ = 3.3v, t a = +25?.) (note 1) parameter symbol conditions min typ max units serial clock frequency f scl 400 khz bus free time between a stop and a start condition t buf 1.3 ? hold time, repeated start condition t hd , sta 0.6 ? repeated start condition setup time t su , sta 0.6 ? stop condition setup time t su , sto 0.6 ? data hold time t hd , dat (note 2) 0.9 ? data setup time t su , dat 180 ns scl clock low period t low 1.3 ? scl clock high period t high 0.7 ? rise time of both sda and scl signals, receiving t r (notes 3, 4) 200 + 0.1c b 300 ns fall time of both sda and scl signals, receiving t f (notes 3, 4) 200 + 0.1c b 300 ns fall time of sda transmitting t f.tx (notes 3, 5) 200 + 0.1c b 250 ns pulse width of spike suppressed t sp (note 6) 50 ns capacitive load for each bus line c b (note 3) 400 pf
max7315 8-port i/o expander with led intensity control, interrupt, and hot-insertion protection 4 _______________________________________________________________________________________ timing characteristics (continued) (typical operating circuit, v+ = 2v to 3.6v, t a = t min to t max , unless otherwise noted. typical values are at v+ = 3.3v, t a = +25?.) (note 1) parameter symbol conditions min typ max units interrupt valid t iv figure 10 6.5 ? interrupt reset t ir figure 10 1 s output data valid t dv figure 10 5 s input data setup time t ds figure 10 100 ns input data hold time t dh figure 10 1 s note 1: all parameters tested at t a = +25?. specifications over temperature are guaranteed by design. note 2: a master device must provide a hold time of at least 300ns for the sda signal (referred to v il of the scl signal) to bridge the undefined region of scl? falling edge. note 3: guaranteed by design. note 4: c b = total capacitance of one bus line in pf. t r and t f measured between 0.3 x v dd and 0.7 x v dd . note 5: i sink 6ma. c b = total capacitance of one bus line in pf. t r and t f measured between 0.3 x v dd and 0.7 x v dd . note 6: input filters on the sda and scl inputs suppress noise spikes less than 50ns. standby current vs. temperature max7315 toc01 temperature ( c) standby current ( a) 110 95 65 80 -10 5 20 35 50 -25 1 2 3 4 5 6 7 8 9 10 0 -40 125 v+ = 3.6v pwm enabled v+ = 2.7v pwm enabled v+ = 2v pwm disabled v+ = 2.7v pwm disabled v+ = 3.6v pwm disabled v+ = 2v pwm enabled supply current vs. temperature (pwm disabled; f scl = 400khz) max7315 toc02 temperature ( c) supply current ( a) 110 95 65 80 -10 5 20 35 50 -25 10 20 30 40 50 60 70 0 -40 125 v+ = 3.6v v+ = 2.7v v+ = 2v 5 10 15 20 25 30 35 40 45 50 55 60 65 70 0 supply current vs. temperature (pwm enabled; f scl = 400khz) max7315 toc03 temperature ( c) supply current ( a) 110 95 65 80 -10 5 20 35 50 -25 -40 125 v+ = 3.6v v+ = 2.7v v+ = 2v __________________________________________typical operating characteristics (t a = +25?, unless otherwise noted.)
max7315 8-port i/o expander with led intensity control, interrupt, and hot-insertion protection _______________________________________________________________________________________ 5 port output low voltage with 50ma load current vs. temperature port output low voltage v ol (v) 0.1 0.2 0.3 0.4 0.5 0.6 0 max7315 toc04 temperature ( c) 110 95 65 80 -10 5 20 35 50 -25 -40 125 v+ = 3.6v v+ = 2.7v v+ = 2v port output low voltage with 20ma load current vs. temperature max7315 toc05 temperature ( c) port output low voltage v ol (v) 110 95 80 65 50 35 20 5 -10 -25 0.1 0.2 0.3 0.4 0.5 0.6 0 -40 125 all outputs loaded v+ = 3.6v v+ = 2.7v v+ = 2v pwm clock frequency vs. temperature max7315 toc06 temperature ( c) pwm clock frequency 110 95 80 65 50 35 20 5 -10 -25 0.950 1.000 1.050 0.900 0.925 0.975 1.025 -40 125 v+ = 3.6v v+ = 2v v+ = 2.7v normalized to v+ = 3.3v, t a = +25 c scope shot of 2 output ports max7315 toc07 2ms/div output 1 2v/div output 2 2v/div master intensity set to 1/15 output 1 individual intensity set to 1/16 output 2 individual intensity set to 15/16 scope shot of 2 output ports max7315 toc08 2ms/div output 1, 2v/div output 2, 2v/div output 1 individual intensity set to 1/16 master intensity set to 14/15 output 2 individual intensity set to 14/15 sink current vs. v ol max7315 toc09 sink current (ma) v ol (v) 50 40 30 20 10 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0 0 v+ = 2v v+ = 2.7v only one output loaded v+ = 3.3v v+ = 3.6v typical operating characteristics (continued) (t a = +25?, unless otherwise noted.)
max7315 functional overview the max7315 is a general-purpose input/output (gpio) peripheral that provides eight i/o ports, p0?7, con- trolled through an i 2 c-compatible serial interface. a 9th output-only port, int /o8, can be configured as an inter- rupt output or as a general-purpose output port. all out- put ports sink loads up to 50ma connected to external supplies up to 5.5v, independent of the max7315? supply voltage. the max7315 is rated for a ground cur- rent of 190ma, allowing all nine outputs to sink 20ma at the same time. figure 1 shows the output structure of the max7315. the ports default to inputs on power-up. port inputs and transition detection an input ports register reflects the incoming logic levels of the port pins, regardless of whether the pin is defined as an input or an output. reading the input 8-port i/o expander with led intensity control, interrupt, and hot-insertion protection 6 _______________________________________________________________________________________ pin qsop/tssop qfn name function 1, 2, 3 15, 16, 1 ad0, ad1, ad2 address inputs. sets device slave address. connect to either gnd, v+, scl, or sda to give 64 logic combinations. see table 1. 4?, 9?2 2?, 7?0 p0?7 input/output ports. p0?7 are open-drain i/os rated at 5.5v, 50ma. 8 6 gnd ground. do not sink more than 190ma into the gnd pin. 13 11 int /o8 output port. open-drain output rated at 7.0v, 50ma. configurable as interrupt output or general-purpose output. 14 12 scl i 2 c-compatible serial clock input 15 13 sda i 2 c-compatible serial data i/o 16 14 v+ positive supply voltage. bypass v+ to gnd with a 0.047? ceramic capacitor pad exposed pad exposed pad on package underside. connect to gnd. pin description figure 1. simplified schematic of i/o ports d c k q q ff data from shift register data from shift register write configuration pulse write pulse read pulse configuration register d c k q q ff input port register d c k q q ff output port register output port register data i/o pin q2 gnd input port register data to int
ports register latches the current-input logic level of the affected eight ports. transition detection allows all ports configured as inputs to be monitored for changes in their logic status. the action of reading the input ports register samples the corresponding 8 port bits input condition. this sample is continuously compared with the actual input conditions. a detected change in input condition causes the int /o8 interrupt output to go low, if configured as an interrupt output. the interrupt is cleared either automatically if the changed input returns to its original state, or when the input ports reg- ister is read. the int /o8 pin can be configured as either an interrupt output or as a 9th output port with the same static or blink controls as the other eight ports (table 4). port output control and led blinking the blink phase 0 register sets the output logic levels of the eight ports p0?7 (table 8). this register controls the port outputs if the blink function is disabled. a duplicate register, the blink phase 1 register, is also used if the blink function is enabled (table 9). in blink mode, the port outputs can be flipped between using the blink phase 0 register and the blink phase 1 regis- ter using software control (the blink flip flag in the con- figuration register) (table 4). pwm intensity control the max7315 includes an internal oscillator, nominally 32khz, to generate pwm timing for led intensity con- trol. pwm intensity control can be enabled on an out- put-by-output basis, allowing the max7315 to provide any mix of pwm led drives and glitch-free logic out- puts (table 10). pwm can be disabled entirely, in which case all output ports are static and the max7315 operating current is lowest because the internal oscilla- tor is turned off. pwm intensity control uses a 4-bit master control and 4 bits of individual control per output (tables 13, 14). the 4-bit master control provides 16 levels of overall intensi- ty control, which applies to all pwm-enabled output ports. the master control sets the maximum pulse width from 1/15 to 15/15 of the pwm time period. the individual settings comprise a 4-bit number further reducing the duty cycle to be from 1/16 to 15/16 of the time window set by the master control. for applications requiring the same pwm setting for all output ports, a single global pwm control can be used instead of all the individual controls to simplify the con- trol software and provide 240 steps of intensity control (tables 10 and 13). standby mode when the serial interface is idle and the pwm intensity control is unused, the max7315 automatically enters standby mode. if the pwm intensity control is used, the operating current is slightly higher because the internal pwm oscillator is running. when the serial interface is active, the operating current also increases because the max7315, like all i 2 c slaves, has to monitor every transmission. serial interface serial addressing the max7315 operates as a slave that sends and receives data through an i 2 c-compatible 2-wire inter- face. the interface uses a serial data line (sda) and a serial clock line (scl) to achieve bidirectional commu- nication between master(s) and slave(s). a master (typ- ically a microcontroller) initiates all data transfers to and from the max7315 and generates the scl clock that synchronizes the data transfer (figure 2). the max7315 sda line operates as both an input and an open-drain output. a pullup resistor, typically 4.7k ? , is required on sda. the max7315 scl line operates max7315 8-port i/o expander with led intensity control, interrupt, and hot-insertion protection _______________________________________________________________________________________ 7 figure 2. 2-wire serial interface timing details scl sda t r t f t buf start condition stop condition repeated start condition start condition t su,sto t hd,sta t su,sta t hd,dat t su,dat t low t high t hd,sta
max7315 only as an input. a pullup resistor, typically 4.7k ? , is required on scl if there are multiple masters on the 2- wire interface, or if the master in a single-master system has an open-drain scl output. each transmission consists of a start condition (figure 3) sent by a master, followed by the max7315 7-bit slave address plus r/ w bit, a register address byte, one or more data bytes, and finally a stop condi- tion (figure 3). start and stop conditions both scl and sda remain high when the interface is not busy. a master signals the beginning of a transmis- sion with a start (s) condition by transitioning sda from high to low while scl is high. when the master has finished communicating with the slave, it issues a stop (p) condition by transitioning sda from low to high while scl is high. the bus is then free for another transmission (figure 3). bit transfer one data bit is transferred during each clock pulse. the data on sda must remain stable while scl is high (figure 4). acknowledge the acknowledge bit is a clocked 9th bit that the recipi- ent uses to handshake receipt of each byte of data (figure 5). thus, each byte transferred effectively requires 9 bits. the master generates the 9th clock pulse, and the recipient pulls down sda during the acknowledge clock pulse so the sda line is stable low during the high period of the clock pulse. when the master is transmitting to the max7315, the device gen- erates the acknowledge bit because the max7315 is the recipient. when the max7315 is transmitting to the master, the master generates the acknowledge bit because the master is the recipient. slave address the max7315 has a 7-bit long slave address (figure 6). the eighth bit following the 7-bit slave address is the r/ w bit. the r/ w bit is low for a write command, high for a read command. the slave address bits a6 through a0 are selected by the address inputs ad0, ad1, and ad2. these pins can be connected to gnd, v+, sda, or scl. the max7315 has 64 possible slave addresses (table 1) and, there- fore, a maximum of 64 max7315 devices can be con- trolled independently from the same interface. message format for writing the max7315 a write to the max7315 comprises the transmission of the max7315? slave address with the r/ w bit set to zero, followed by at least 1 byte of information. the first byte of information is the command byte. the command byte determines which register of the max7315 is to be written to by the next byte, if received (table 2). if a stop condition is detected after the command byte is received, then the max7315 takes no further action beyond storing the command byte. 8-port i/o expander with led intensity control, interrupt, and hot-insertion protection 8 _______________________________________________________________________________________ figure 3. start and stop conditions sda scl start condition stop condition sp figure 4. bit transfer sda scl data line stable; data valid change of data allowed figure 5. acknowledge scl sda by transmitter clock pulse for acknowledge start condition sda by receiver 12 89 s figure 6. slave address sda scl a5 msb lsb ack a4 a1 a6 a3 a0 a2 r/w
max7315 8-port i/o expander with led intensity control, interrupt, and hot-insertion protection _______________________________________________________________________________________ 9 table 1. max7315 i 2 c slave address map device address pin ad2 pin ad1 pin ad0 a6 a5 a4 a3 a2 a1 a0 gnd scl gnd0010000 gnd scl v+ 0010001 gndsda gnd0010010 gndsda v+ 0010011 v+ scl gnd0010100 v+ scl v+ 0010101 v+ sda gnd0010110 v+ sda v+ 0010111 gnd scl scl 0011000 gnd scl sda0011001 gndsda scl 0011010 gndsda sda0011011 v+ scl scl 0011100 v+ scl sda0011101 v+ sda scl 0011110 v+ sda sda0011111 gndgndgnd0100000 gndgnd v+ 0100001 gnd v+ gnd0100010 gnd v+ v+ 0100011 v+ gndgnd0100100 v+ gnd v+ 0100101 v+ v+ gnd0100110 v+ v+ v+ 0100111 gndgnd scl 0101000 gndgndsda0101001 gnd v+ scl 0101010 gnd v+ sda0101011 v+ gnd scl 0101100 v+ gndsda0101101 v+ v+ scl 0101110 v+ v+ sda0101111
max7315 8-port i/o expander with led intensity control, interrupt, and hot-insertion protection 10 ______________________________________________________________________________________ table 1. max7315 i 2 c slave address map (continued) device address pin ad2 pin ad1 pin ad0 a6 a5 a4 a3 a2 a1 a0 scl scl gnd1010000 scl scl v+ 1010001 scl sda gnd1010010 scl sda v+ 1010011 sda scl gnd1010100 sda scl v+ 1010101 sda sda gnd1010110 sda sda v+ 1010111 scl scl scl 1011000 scl scl sda1011001 scl sda scl 1011010 scl sda sda1011011 sda scl scl 1011100 sda scl sda1011101 sda sda scl 1011110 sda sda sda1011111 scl gndgnd1100000 scl gnd v+ 1100001 scl v+ gnd1100010 scl v+ v+ 1100011 sda gndgnd1100100 sda gnd v+ 1100101 sda v+ gnd1100110 sda v+ v+ 1100111 scl gnd scl 1101000 scl gndsda1101001 scl v+ scl 1101010 scl v+ sda1101011 sda gnd scl 1101100 sda gndsda1101101 sda v+ scl 1101110 sda v+ sda1101111
any bytes received after the command byte are data bytes. the first data byte goes into the internal register of the max7315 selected by the command byte (figure 8). if multiple data bytes are transmitted before a stop condition is detected, these bytes are generally stored in subsequent max7315 internal registers because the command byte address autoincrements (table 2). a diagram of a write to the output ports registers (blink phase 0 register or blink phase 1 register) is given in figure 10. message format for reading the max7315 is read using the max7315? internally stored command byte as an address pointer the same way the stored command byte is used as an address pointer for a write. the pointer autoincrements after each data byte is read using the same rules as for a write (table 2). thus, a read is initiated by first configur- ing the max7315? command byte by performing a write (figure 7). the master can now read n consecu- tive bytes from the max7315 with the first data byte being read from the register addressed by the initial- ized command byte. when performing read-after-write verification, remember to reset the command byte? address because the stored command byte address has been autoincremented after the write (table 2). a diagram of a read from the input ports register is shown in figure 10 reflecting the states of the ports. operation with multiple masters if the max7315 is operated on a 2-wire interface with multiple masters, a master reading the max7315 should use a repeated start between the write, which sets the max7315? address pointer, and the read(s) that takes the data from the location(s) (table 2). this is because it is possible for master 2 to take over the bus after master 1 has set up the max7315? address pointer but before master 1 has read the data. if master 2 subsequently changes the max7315? address pointer, then master 1? delayed read can be from an unexpect ed location. max7315 8-port i/o expander with led intensity control, interrupt, and hot-insertion protection ______________________________________________________________________________________ 11 figure 8. command and single data byte received saaap 0 slave address command byte data byte 1 byte autoincrement memory address d15 d14 d13 d12 d11 d10 d9 d8 d1 d0 d3 d2 d5 d4 d7 d6 acknowledge from max7315 acknowledge from max7315 acknowledge from max7315 how command byte and data byte map into max7315's registers r/w figure 9. n data bytes received saaap 0 slave address command byte data byte n bytes autoincrement memory address d15 d14 d13 d12 d11 d10 d9 d8 d1 d0 d3 d2 d5 d4 d7 d6 acknowledge from max7315 acknowledge from max7315 acknowledge from max7315 how command byte and data byte map into max7315's registers r/w figure 7. command byte received saa p 0 slave address command byte acknowledge from max7315 d15 d14 d13 d12 d11 d10 d9 d8 command byte is stored on receipt of stop condition acknowledge from max7315 r/w
max7315 command address autoincrementing the command address stored in the max7315 circu- lates around grouped register functions after each data byte is written or read (table 2). device reset if a device reset input is needed, consider the max7316. the max7316 includes a rst input, which clears any transaction to or from the max7316 on the serial interface and configures the internal registers to the same state as a power-up reset. detailed description initial power-up on power-up all control registers are reset and the max7315 enters standby mode (table 3). power-up status makes all ports into inputs and disables both the pwm oscillator and blink functionality. configuration register the configuration register is used to configure the pwm intensity mode, interrupt, and blink behavior, operate the int /o8 output, and read back the interrupt status (table 4). 8-port i/o expander with led intensity control, interrupt, and hot-insertion protection 12 ______________________________________________________________________________________ figure 10. read, write, and interrupt timing diagrams slave address 123456789 sa6a5a4a3a2a1a00a0 000000 command byte 1a a ap start condition acknowledge from slave acknowledge from slave acknowledge from slave stop condition p7?0 data1 valid data2 valid slave address 123456789 s a6a5a4a3a2a1a0 1 a command byte ana start condition acknowledge from slave acknowledge from master p7?0 stop condition p no acknowledge from master data2 data3 t dv t dv slave address 123456789 sa6a5a4a3a2a1a0 1 a command byte ana start condition acknowledge from slave acknowledge from master p7?0 stop condition p no acknowledge from master data1 data2 data3 data4 t dh t ds data1 t iv t ir t ir t iv scl sda scl sda scl sda write to output ports registers (blink phase 0 registers/blink phase 1 registers) read from input ports registers interrupt valid/reset r/w msb lsb data1 msb lsb data1 msb lsb data2 msb lsb data4 msb lsb data4 msb lsb data2 r/w r/w int
ports configuration the 8 i/o ports p0 through p7 can be configured to any combination of inputs and outputs using the ports con- figuration register (table 5). the int /o8 output can also be configured as an extra general-purpose output using the configuration register (table 4). input ports the input ports register is read only (table 6). it reflect the incoming logic levels of the ports, regardless of whether the port is defined as an input or an output by the ports configuration register. reading the input ports register latches the current-input logic level of the affected eight ports. a write to the input ports register is ignored. transition detection all ports configured as inputs are always monitored for changes in their logic status. the action of reading the input ports register or writing to the configuration regis- ter samples the corresponding 8 port bits?input condi- tion (tables 4, 6). this sample is continuously compared with the actual input conditions. a detected change in input condition causes an interrupt condition. the interrupt is cleared either automatically if the changed input returns to its original state, or when the input ports register is read, updating the compared data (figure 10). randomly changing a port from an output to an input may cause a false interrupt to occur if the state of the input does not match the content of the input ports register. the interrupt status is available as the interrupt flag int in the configuration register (table 4). the input status of all ports is sampled immediately after power-up as part of the max7315? internal initial- ization, so if all the ports are pulled to valid logic levels at that time an interrupt does not occur at power-up. int /o8 output the int /o8 output pin can be configured as either the int output that reflects the interrupt flag logic state or as a general-purpose output o8. when used as a general- purpose output, the int /o8 pin has the same blink and pwm intensity control capabilities as the other ports. set the interrupt enable i bit in the configuration register to configure int /o8 as the int output (table 4). clear interrupt enable to configure int /o8 as the o8. o8 logic state is set by the 2 bits o1 and o0 in the configu- ration register. o8 follows the rules for blinking selected by the blink enable flag e in the configuration register. if blinking is disabled, then interrupt output control o0 alone sets the logic state of the int /o8 pin. if blinking is enabled, then both interrupt output controls o0 and o1 set the logic state of the int /o8 pin according to the blink phase. pwm intensity control for o8 is set by the 4 global intensity bits in the master, o8 intensity register (table 13). blink mode in blink mode, the output ports can be flipped between using either the blink phase 0 register or the blink phase 1 register. flip control is by software control (the blink flip flag b in the configuration register) (table 4). if hardware flip control is needed, consider the max7316, which includes a blink input, as well as software control. the blink function can be used for led effects by pro- gramming different display patterns in the two sets of max7315 8-port i/o expander with led intensity control, interrupt, and hot-insertion protection ______________________________________________________________________________________ 13 table 2. register address map register address code (hex) autoincrement address read input ports 0x00 0x00 (no change) blink phase 0 outputs 0x01 0x01 (no change) ports configuration 0x03 0x03 (no change) blink phase 1 outputs 0x09 0x09 (no change) master, o8 intensity 0x0e 0x0e (no change) configuration 0x0f 0x0f (no change) outputs intensity p1, p0 0x10 0x11 outputs intensity p3, p2 0x11 0x12 outputs intensity p5, p4 0x12 0x13 outputs intensity p7, p6 0x13 0x10
max7315 8-port i/o expander with led intensity control, interrupt, and hot-insertion protection 14 ______________________________________________________________________________________ table 3. power-up configuration register data register function power-up condition address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 blink phase 0 outputs p7?0 high-impedance outputs 0x01 1 1 1 1 1 1 1 1 ports configuration p7?0 ports p7?0 are inputs 0x03 1 1 1 1 1 1 1 1 blink phase 1 outputs p7?0 high-impedance outputs 0x09 1 1 1 1 1 1 1 1 master, o8 intensity pwm oscillator is disabled; o8 is static logic output 0x0e 0 0 0 0 1 1 1 1 configuration int /o8 is interrupt output; blink is disabled; global intensity is enabled 0x0f 0 0 0 0 1 1 0 0 outputs intensity p1, p0 p1, p0 are static logic outputs 0x10 1 1 1 1 1 1 1 1 outputs intensity p3, p2 p3, p2 are static logic outputs 0x11 1 1 1 1 1 1 1 1 outputs intensity p5, p4 p5, p4 are static logic outputs 0x12 1 1 1 1 1 1 1 1 outputs intensity p7, p6 p7, p6 are static logic outputs 0x13 1 1 1 1 1 1 1 1 table 4. configuration register register data register address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 configuration r/ w interrupt status interrupt output control as gpo interrupt enable global intensity blink flip blink enable write device configuration 0 x read-back device configuration 1 int o o1 o0 i g b e disable blink xxxxxxx 0 enable blink xxxxxxx 1 xxxxxx 01 flip blink register (see text) xxxxxx 11 disable global intensity control?ntensity is set by registers 0x10?x13 for ports p0 through p7 when configured as outputs, and by d3?7 of register 0x0e for int /o8 when int /o8 pin is configured as an output port xxxxx 0 xx enable global intensity control?ntensity for all ports configured as outputs is set by d3?0 of register 0x0e 0x0f xxxxx 1 xx x = don? care.
output port registers, and using the software or hard- ware controls to flip between the patterns. if the blink phase 1 register is written with 0xff, then the blink input can be used as a hardware disable to, for example, instantly turn off an led pattern pro- grammed into the blink phase 0 register. this tech- nique can be further extended by driving the blink input with a pwm signal to modulate the led current to provide fading effects. the blink mode is enabled by setting the blink enable flag e in the configuration register (table 4). when blink mode is enabled, the state of the blink flip flag sets the phase, and the output ports are set by either the blink phase 0 register or the blink phase 1 register (table 7). the blink mode is disabled by clearing the blink enable flag e in the configuration register (table 4). when blink mode is disabled, the blink phase 0 register alone con- trols the output ports. blink phase registers when the blink function is disabled, the blink phase 0 register sets the logic levels of the 8 ports (p0 through p7) when configured as outputs (table 8). a duplicate register called the blink phase 1 reg ister is also used if the blink function is enabled (table 9). a logic high sets the appropriate output port high impedance, while a logic low makes the port go low. max7315 8-port i/o expander with led intensity control, interrupt, and hot-insertion protection ______________________________________________________________________________________ 15 table 4. configuration register (continued) register data register address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 configuration r/ w interrupt status interrupt output control as gpo interrupt enable global intensity blink flip blink enable x disable data change interrupt int /o8 output is controlled by the o0 and o1 bits int o o1 o0 i g b e enable data change interrupt int /o8 output is controlled by port input data change xxxx 1 xxx int /o8 output is low (blink is disabled) xxx 00 xx 0 int /o8 output is high impedance (blink is disabled) xxx 10 xx 0 int /o8 outp ut i s l ow d ur i ng b l i nk p hase 0 xxx 00 xx 1 int /o8 output is high impedance during blink phase 0 xxx 10 xx 1 int /o8 outp ut i s l ow d ur i ng b l i nk p hase 1 xx 0 x 0 xx 1 int /o8 output is high impedance during blink phase 1 xx 1 x 0 xx 1 read-back data change interrupt status ?ata change is not detected, and int /o8 output is high when interrupt enable (i bit) is set 1 0 0xxxxxx read-back data change interrupt status ?ata change is detected, and int /o8 output is low when interrupt enable (i bit) is set 1 0x0f 1 0xxxxxx x = don? care.
max7315 reading a blink phase register reads the value stored in the register, not the actual port condition. the port output itself may or may not be at a valid logic level, depending on the external load connected. the 9th output, o8, is controlled through 2 bits in the configuration register, which provide the same static or blink control as the other 8 output ports. pwm intensity control the max7315 includes an internal oscillator, nominally 32khz, to generate pwm timing for led intensity con- trol or other applications such as pwm trim dacs. pwm can be disabled entirely for all the outputs. in this case, all outputs are static and the max7315 operating cur- rent is lowest because the internal pwm oscillator is turned off. the max7315 can be configured to provide any combi- nation of pwm outputs and glitch-free logic outputs. each pwm output has an individual 4-bit intensity con- trol (table 14). when all outputs are to be used with the same pwm setting, the outputs can be controlled together instead using the global intensity control (table 13). table 10 shows how to set up the max7315 to suit a particular application. pwm timing the pwm control uses a 240-step pwm period, divided into 15 master intensity timeslots. each master intensity timeslot is divided further into 16 pwm cycles (figure 11). the master intensity operates as a gate, allowing the indi- vidual output settings to be enabled from 1 to 15 timeslots per pwm period (figures 12, 13, 14) (table 13). each output? individual 4-bit intensity control only operates during the number of timeslots gated by the master intensity. the individual controls provide 16 intensity settings from 1/16 through 16/16 (table 14). figures 15, 16, and 17 show examples of individual intensity control settings. the highest value an individ- ual or global setting can be set to is 16/16. this setting forces the output to ignore the master control, and fol- low the logic level set by the appropriate blink phase register bit. the output becomes a glitch-free static out- put with no pwm. using pwm intensity controls with blink disabled when blink is disabled (table 7), the blink phase 0 reg- ister specifies each output? logic level during the pwm on-time (table 8). the effect of setting an output? blink phase 0 register bit to 0 or 1 is shown in table 11. with its output bit set to zero, an led can be controlled with 16 intensity settings from 1/16th duty through fully on, but cannot be turned fully off using the pwm intensity control. with its output bit set to 1, an led can be con- trolled with 16 intensity settings from fully off through 15/16th duty. 8-port i/o expander with led intensity control, interrupt, and hot-insertion protection 16 ______________________________________________________________________________________ table 5. ports configuration register register data register r/ w address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 ports configuration (1 = input, 0 = output) 0 read-back ports configuration 1 0x03 op7 op6 op5 op4 op3 op2 op1 op0 table 6. input ports register register data register r/ w address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 read input ports 1 0x00 ip7 ip6 ip5 ip4 ip3 ip2 ip1 ip0 table 7. blink controls blink enable flag e blink flip flag b blink function output registers used 0 x disabled blink phase 0 register 0 blink phase 0 register 1 1 enabled blink phase 1 register x = don? care.
using pwm intensity controls with blink enabled when blink is enabled (table 7), the blink phase 0 regis- ter and blink phase 1 register specify each output? logic level during the pwm on-time during the respective blink phases (tables 8 and 9). the effect of setting an output? blink phase x register bit to 0 or 1 is shown in table 12. leds can be flipped between either directly on and off, or between a variety of high/low pwm intensities. global/o8 intensity control the 4 bits used for output o8? pwm individual intensity setting also double as the global intensity control (table 13). global intensity simplifies the pwm settings when the application requires them all to be the same, such as for backlight applications, by replacing the 9 individual settings with 1 setting. global intensity is enabled with the global intensity flag g in the configu- ration register (table 4). when global pwm control is used, the 4 bits of master intensity and 4 bits of o8 intensity effectively combine to provide an 8 bit, 240- step intensity control applying to all outputs. it is not possible to apply global pwm control to a sub- set of the ports, and use the others as logic outputs. to mix static logic outputs and pwm outputs, individual pwm control must be selected (table 10). applications information hot insertion i/o ports po-p7, interrupt output int /08, and serial interface sda, scl, ad0-2 remain high impedance with up to 6v asserted on them when the max7315 is powered down (v+ = 0v). the max7315 can therefore be used in hot-swap applications. output level translation the open-drain output architecture allows the ports to level translate the outputs to higher or lower voltages than the max7315 supply. an external pullup resistor can be used on any output to convert the high-imped- ance logic-high condition to a positive voltage level. the resistor can be connected to any voltage up to 5.5v. for interfacing cmos inputs, a pullup resistor value of 220k ? is a good starting point. use a lower resistance to improve noise immunity, in applications where power consumption is less critical, or where a faster rise time is needed for a given capacitive load. compatibility with pca9534 and pca9554(a) the max7315 is pin compatible and software compatible with pca9534, and its variants pca9554 and pca9554a. however, some pca9534 and pca9554(a) functions are not implemented in the max7315, and the max7315's pwm and blink functionality is not supported in the pca9534 and pca9554(a). software compatibility is clearly not 100%, but the max7315 was designed so the subset (omitted) features default to the same power- up behavior as the pca9534 and pca9554(a), and the superset features do not use existing registers in a differ- ent way. in practice, many applications can use the max7315 as a drop-in replacement for the pca9534 or pca9554(a) with no software change. driving led loads when driving leds, a resistor in series with the led must be used to limit the led current to no more than 50ma. choose the resistor value according to the fol- lowing formula: r led = (v supply - v led - v ol ) / i led max7315 8-port i/o expander with led intensity control, interrupt, and hot-insertion protection ______________________________________________________________________________________ 17 table 8. blink phase 0 register register data register r/ w address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 write outputs phase 0 0 read-back outputs phase 0 1 0x01 op7 op6 op5 op4 op3 op2 op1 op0 table 9. blink phase 1 register register data register r/ w address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 write outputs phase 1 0 read-back outputs phase 1 1 0x09 op7 op6 op5 op4 op3 op2 op1 op0
max7315 8-port i/o expander with led intensity control, interrupt, and hot-insertion protection 18 ______________________________________________________________________________________ table 10. pwm application scenarios application recommended configuration all outputs static without pwm set the master, o8 intensity register 0x0e to any value from 0x00 to 0x0f. the global intensity g bit in the configuration register is don't care. the output intensity registers 0x10 through 0x13 are don't care. a mix of static and pwm outputs, with pwm outputs using different pwm settings set the master, o8 intensity register 0x0e to any value from 0x10 to 0xff. clear global intensity g bit to 0 in the configuration register to disable global intensity control. for the static outputs, set the output intensity value to 0xf. for the pwm outputs, set the output intensity value in the range 0x0 to 0xe. a mix of static and pwm outputs, with pwm outputs all using the same pwm setting as above. global intensity control cannot be used with a mix of static and pwm outputs, so write the individual intensity registers with the same pwm value. all outputs pwm using the same pwm setting set the master, o8 intensity register 0x0e to any value from 0x10 to 0xff. set global intensity g bit to 1 in the configuration register to enable global intensity control. the master, o8 intensity register 0x0e is the only intensity register used. the output intensity registers 0x10 through 0x13 are don't care. figure 11. pwm timing one pwm period is 240 cycles of the 32khz pwm oscillator. a pwm period contains 15 master intensity timeslots 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 14 15 1 2 each master intensity timeslot contains 16 pwm cycles 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 15 16 1 2 figure 12. master set to 1/15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 14 15 2 1 . figure 14. master set to 15/15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 14 15 2 1 . . figure 13. master set to 14/15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 14 15 2 1 . .
max7315 8-port i/o expander with led intensity control, interrupt, and hot-insertion protection ______________________________________________________________________________________ 19 figure 16. individual (or global) set to 15/16 master intensity timeslot 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 next master intensity timeslot 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 figure 15. individual (or global) set to 1/16 master intensity timeslot 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 next master intensity timeslot 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 figure 17. individual (or global) set to 16/16 master intensity timeslot control is ignored 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 table 11. pwm intensity settings (blink disabled) pwm duty cycle output blink phase 0 register bit = 0 pwm duty cycle output blink phase 0 register bit = 1 output (or global) intensity setting low time high time led behavior when output blink phase 0 register bit = 0 (led is on when output is low) low time high time led behavior when output blink phase 0 register bit = 1 (led is on when output is low) 0x0 1/16 15/16 lowest pwm intensity 15/16 1/16 highest pwm intensity 0x1 2/16 14/16 14/16 2/16 0x2 3/16 13/16 13/16 3/16 0x3 4/16 12/16 12/16 4/16 0x4 5/16 11/16 11/16 5/16 0x5 6/16 10/16 10/16 6/16 0x6 7/16 9/16 9/16 7/16 0x7 8/16 8/16 8/16 8/16 0x8 9/16 7/16 7/16 9/16 0x9 10/16 6/16 6/16 10/16 0xa 11/16 5/16 5/16 11/16 0xb 12/16 4/16 4/16 12/16 0xc 13/16 3/16 3/16 13/16 0xd 14/16 2/16 increasing pwm intensity 2/16 14/16 increasing pwm intensity 0xe 15/16 1/16 highest pwm intensity 1/16 15/16 lowest pwm intensity 0xf static low static low full intensity, no pwm (led on continuously) static high impedance static high impedance led off continuously
max7315 where: r led is the resistance of the resistor in series with the led ( ? ). v supply is the supply voltage used to drive the led (v). v led is the forward voltage of the led (v). v ol is the output low voltage of the max7315 when sinking i led (v). i led is the desired operating current of the led (a). for example, to operate a 2.2v red led at 14ma from a 5v supply, r led = (5 - 2.2 - 0.25) / 0.014 = 182 ? . driving load currents higher than 50ma the max7315 can be used to drive loads drawing more than 50ma, like relays and high-current white leds, by paralleling outputs. use at least one output per 50ma of load current; for example, a 5v 330mw relay draws 66ma and needs two paralleled outputs to drive it. ensure that the paralleled outputs chosen are controlled by the same blink phase register, i.e., select outputs from the p0 through p7 range. this way, the paralleled outputs are turned on and off together. do not use out- put o8 as part of a load-sharing design. o8 cannot be switched at the same time as any of the other outputs because it is controlled by a different register. the max7315 must be protected from the negative voltage transient generated when switching off induc- tive loads, such as relays, by connecting a reverse- biased diode across the inductive load (figure 18). the peak current through the diode is the inductive load? operating current. power-supply considerations the max7315 operates with a power-supply voltage of 2v to 3.6v. bypass the power supply to gnd with at least 0.047? as close to the device as possible. for the qfn version, connect the underside exposed pad to gnd. chip information transistor count: 17,611 process: bicmos 8-port i/o expander with led intensity control, interrupt, and hot-insertion protection 20 ______________________________________________________________________________________ table 12. pwm intensity settings (blink enabled) examples of led blink behavior (led is on when output is low) pwm duty cycle output blink phase x register bit = 0 pwm duty cycle output blink phase x register bit = 1 output (or global) intensity setting low time high time low time high time blink phase 0 register bit = 0 blink phase 1 register bit = 1 blink phase 0 register bit = 1 blink phase 1 register bit = 0 0x0 1/16 15/16 15/16 1/16 0x1 2/16 14/16 14/16 2/16 0x2 3/16 13/16 13/16 3/16 0x3 4/16 12/16 12/16 4/16 0x4 5/16 11/16 11/16 5/16 0x5 6/16 10/16 10/16 6/16 0x6 7/16 9/16 9/16 7/16 p hase 0: le d on at l ow i ntensi ty p hase 1: le d on at hi g h i ntensi ty p hase 0: le d on at hi g h i ntensi ty p hase 1: le d on at l ow i ntensi ty 0x7 8/16 8/16 8/16 8/16 output is half intensity during both blink phases 0x8 9/16 7/16 7/16 9/16 0x9 10/16 6/16 6/16 10/16 0xa 11/16 5/16 5/16 11/16 0xb 12/16 4/16 4/16 12/16 0xc 13/16 3/16 3/16 13/16 0xd 14/16 2/16 2/16 14/16 0xe 15/16 1/16 1/16 15/16 p hase 0: le d on at hi g h i ntensi ty p hase 1: le d on at l ow i ntensi ty p hase 0: le d on at l ow i ntensi ty p hase 1: le d on at hi g h i ntensi ty 0xf static low static low static high impedance static high impedance phase 0: led on continuously phase 1: led off continuously phase 0: led off continuously phase 1: led on continuously
max7315 8-port i/o expander with led intensity control, interrupt, and hot-insertion protection ______________________________________________________________________________________________________ 21 table 13. master, o8 intensity register register data register address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 msb lsb msb lsb master and global intensity r/ w master intensity o8 intensity write master and global intensity 0 read back master and global intensity 1 m3 m2 m1 m0 g3 g2 g1 g0 master intensity duty cycle is 0/15 (off); internal oscillator is disabled; all outputs will be static with no pwm 0000 master intensity duty cycle is 1/15 0001 master intensity duty cycle is 2/15 0010 master intensity duty cycle is 3/15 0011 master intensity duty cycle is 13/15 1101 master intensity duty cycle is 14/15 1110 master intensity duty cycle is 15/15 (full) 1111 o8 intensity duty cycle is 1/16 0 0 0 0 o8 intensity duty cycle is 2/16 0 0 0 1 o8 intensity duty cycle is 3/16 0 0 1 0 o8 intensity duty cycle is 14/16 1 1 0 1 o8 intensity duty cycle is 15/16 1 1 1 0 o8 intensity duty cycle is 16/16 (static output, no pwm) 0x0e 1 1 1 1
max7315 8-port i/o expander with led intensity control, interrupt, and hot-insertion protection 22 ______________________________________________________________________________________ table 14. output intensity registers register data register address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 msb lsb msb lsb outputs p1, p0 intensity r/ w ttintnit ttintnit write output p1, p0 intensity 0 read back output p1, p0 intensity 1 p1i3 p1i2 p1i1 p1i0 p0i3 p0i2 p0i1 p0i0 output p1 intensity duty cycle is 1/16 0000 output p1 intensity duty cycle is 2/16 0001 output p1 intensity duty cycle is 3/16 0010 output p1 intensity duty cycle is 14/16 1101 output p1 intensity duty cycle is 15/16 1110 output p1 intensity duty cycle is 16/16 (static logic level, no pwm) 1111 output p0 intensity duty cycle is 1/16 0 0 0 0 output p0 intensity duty cycle is 2/16 0 0 0 1 output p0 intensity duty cycle is 3/16 0 0 1 0 output p0 intensity duty cycle is 14/16 1 1 0 1 output p0 intensity duty cycle is 15/16 1 1 1 0 output p0 intensity duty cycle is 16/16 (static logic level, no pwm) 0x10 1 1 1 1 msb lsb msb lsb outputs p3, p2 intensity output p3 intensity output p2 intensity write output p3, p2 intensity 0 read back output p3, p2 intensity 1 0x11 p3i3 p3i2 p3i1 p3i0 p2i3 p2i2 p2i1 p2i0 msb lsb msb lsb outputs p5, p4 intensity output p5 intensity output p4 intensity write output p5, p4 intensity 0 read back output p5, p4 intensity 1 0x12 p5i3 p5i2 p5i1 p5i0 p4i3 p4i2 p4i1 p4i0 msb lsb msb lsb outputs p7, p6 intensity output p7 intensity output p6 intensity write output p7, p6 intensity 0 read back output p7, p6 intensity 1 0x13 p7i3 p7i2 p7i1 p7i0 p6i3 p6i2 p6i1 p6i0 output o8 intensity see the master, o8 intensity register (table 13).
max7315 8-port i/o expander with led intensity control, interrupt, and hot-insertion protection ______________________________________________________________________________________ 23 table 15. max7311, pca9535, and pca9555 register compatibility pca9534, pca9554(a) register address max7313 implementation max7311, pca9535, pca9555 implementation comments inputs 0x00 inputs registers implemented same functionality outputs 0x01 blink phase 0 registers implemented same functionality polarity inversion 0x02 not implemented; register writes are ignored; register reads return 0x00 implemented; power-up default is 0x00 if polarity inversion feature is unused, max7313 defaults to correct state configuration 0x03 ports configuration registers not implemented same functionality no registers 0x0b blink phase 1 registers not implemented no register 0x0e master and global/o8 intensity register not implemented no register 0x0f configuration register not implemented no registers 0x10?x13 outputs intensity registers not implemented power-up default disables the blink and intensity (pwm) features figure 18. diode-protected switching inductive load max7315 p0 p1 p2 p3 p4 p5 p6 p7 v+ 2v to 3.6v c sda scl sda i/o ad0 scl gnd ad2 ad1 0.047 f int/o8 bas16 5v 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 ad0 v+ sda scl p7 p6 p5 p4 top view max7315aee max7315aue qsop/tssop ad1 ad2 p2 p0 p1 p3 gnd int/o8 pin configurations (continued) max7315 p5 p0 p1 p2 p3 v+ 3.3v c sda scl sda i/o ad0 5v 3.3v p6 p7 scl p4 output2 output1 gnd 5v input 1 input 2 ad2 ad1 0.047 f int/o8 typical application circuit
max7315 8-port i/o expander with led intensity control, interrupt, and hot-insertion protection 24 ______________________________________________________________________________________ qsop.eps e 1 1 21-0055 package outline, qsop .150", .025" lead pitch package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max7315 8-port i/o expander with led intensity control, interrupt, and hot-insertion protection ______________________________________________________________________________________ 25 package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 12x16l qfn thin.ep s 0.10 c 0.08 c 0.10 m c a b d d/2 e/2 e a1 a2 a e2 e2/2 l k e (nd - 1) x e (ne - 1) x e d2 d2/2 b l e l c l e c l l c l c e 1 2 21-0136 package outline 12, 16l, thin qfn, 3x3x0.8mm 1. dimensioning & tolerancing conform to asme y14.5m-1994. exposed pad variations 2. all dimensions are in millimeters. angles are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 5. dimension b applies to metallized terminal and is measured between 0.20 mm and 0.25 mm from terminal tip. 6. nd and ne refer to the number of terminals on each d and e side respectively. 7. depopulation is possible in a symmetrical fashion. 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 9. drawing conforms to jedec mo220 revision c. notes: e 2 2 21-0136 package outline 12, 16l, thin qfn, 3x3x0.8mm down bonds allowed
max7315 8-port i/o expander with led intensity control, interrupt, and hot-insertion protection maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 26 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products. tssop4.40mm.eps package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)

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